The pin combinations to be used are given in Table 2. The actual number of pin combination sets
depends on the number of power pin groups. Power pins and Power Pin Groups are defined in 4.5.
Programming pins that do not draw current should be considered as I/O pins (example: Vpp pins on
memory devices). Active discrete devices (FETs, transistors, etc.) shall be tested using all possible pin-
pair combinations (one pin connected to Terminal A, another pin connected to Terminal B) regardless of
pin name or function. All pins which are not connected to the die shall be verified as such and left open
(floating) at all times. Pins labeled as “no connect” that are electrically connected to the die shall be tested
as non-supply I/O pins
The pin combinations to be used are given in Table 2. The actual number of pin combination sets
depends on the number of power pin groups. Power pins and Power Pin Groups are defined in 4.5.
Programming pins that do not draw current should be considered as I/O pins (example: Vpp pins on
memory devices). Active discrete devices (FETs, transistors, etc.) shall be tested using all possible pin-
pair combinations (one pin connected to Terminal A, another pin connected to Terminal B) regardless of
pin name or function. All pins which are not connected to the die shall be verified as such and left open
(floating) at all times. Pins labeled as “no connect” that are electrically connected to the die shall be tested
as non-supply I/O pins
感谢楼主支持学习，万万感激